AP-101

The IBM AP-101 is an avionics computer, used most notably in the U.S. space shuttle, but also in the B-52 bomber among others. When it was designed, it was a high-performance pipelined processor with core memory. As of 2003, its specifications are exceeded by many microprocessors.

The AP-101 shares its general architecture with the System/360 and 4Pi computers. It has 16 32-bit registers, and uses a microprogram to define an instruction set of 154 instructions. Originally only 16 bits were available for addressing memory; later this was extended with four bits from the program status word register, allowing a directly addressable memory range of 1M locations.

The original AP-101 was built using TTL integrated circuits. The main memory was originally core memory, but the AP-101S upgrade in the early 1990s used semiconductor memory.

A shuttle uses five AP-101s as "general-purpose computers" (GPCs). Four operate in sync, for redundancy, while the fifth is a backup running software written independently. The shuttle software is written in HAL/S, a special-purpose high-level language, whereas AP-101s used by the US Air Force are mostly programmed in JOVIAL.

References

• Norman, P. Glenn (IBM Corp.). The new AP101S General-Purpose Computer (GPC) for the Space Shuttle. In IEEE Proceedings, Volume 75, Page 308-319, Mar 01, 1987.

External links

• NASA description of shuttle GPCs
• NASA history of AP-101 development