The initial ASICs were implemented using gate-array technology.
Perhaps the first gate-array was the ULA (Uncommitted Logic Array) produced by British firm Ferranti around 1980. These were customised by varying the metal interconnect mask. They had complexities of up to a few thousand gates. Later versions were generalized with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.
In the late 1980's, the availability of silicon compilers such as Design Compiler that could accept hardware description language descriptions using Verilog and VHDL and compile the logic into to a gate level netlist brought "standard-cell" design into the fore-front. A standard-cell library consists of pre-characterized collections of gates such as 2 input nor, 2 input nand, invertors, etc. that are employed by the silicon compiler to translate the original source into a gate level netlist. This netlist is fed into place and routing applications that then place the pre-characterized cells in a matrix fashion, and then the connections are then routed through the matrix. The final output of the place & route process is a data-base representing the various layers and polygons in GDS-II format that represent the different mask-layers of the actual chip.
Finally, there is also the "full-custom" route in implementing an ASIC. This is where each transistor is individually described in building the circuit. It isn't unusual to see a "full-custom" implementation function 5 times faster than a "standard-cell" implementation. The "standard-cell" implementation can usually be implemented quite a bit quicker than the "full-custom" choice.
As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) has increased from 5000 gates to 20 million or more. Modern ASICs often include 32-bit processors and other large building-blocks. These ASICs are often referred to as SoC - System on a Chip.
A growing trend in ASICs is the use of intellectual property or IP. Many ASIC houses have had standard cell libraries for years. However IP takes the reuse of designs to a new level. Most complex digital ICs are now designed with computer languages that describe electronics rather than code. Many organizations now sell tested functional blocks written in these languages. For example, one can purchase CPU's, Ethernet or telephone interfaces.
For smaller designs and/or lower production volumes, ASICs are becoming a less attractive solution, as field-programmable gate arrays (FPGAs) grow larger, faster and more capable. Some SoCs consist of a microprocessor, various types of memory and a large FPGA.
See also: embedded system