Some of these input/output tasks can be fairly complex and require logic to be applied to the data to convert formats and other similar duties. In these situations the computer's CPU would normally be asked to handle the logic, but due to the fact that the I/O devices are very slow, the CPU would end up spending a huge amount of time (in computer terms) sitting idle waiting for the data from the device.
A channel controller avoids this problem by using a low-cost CPU with enough logic and memory onboard to handle these sorts of tasks. They are typically not powerful or flexible enough to be used on their own, and are actually a form of co-processor. The CPU sends small programs to the controller to handle an I/O job, which the channel controller can then complete without any help from the CPU. When it is complete, or there is an error, the channel controller communicates with the CPU using a selection of interrupts.
Since the channel controller has direct access to the main memory of the computer, they are also often referred to as DMA Controllers (where DMA means direct memory access), but that term is somewhat more loose in definition and is often applied to non-programmable devices as well.
The first use of channel controllers was in the famed CDC 6600 supercomputer, which used 12 dedicated computers for this role. Since the 1960s channel controllers have been a standard part of almost all mainframe designs, and the primary reason why anyone buys one. Channel controllers have also been made as small as single-chip designs with multiple channels on them, used in the NeXT computers for instance. However with the rapid speed increases in computers today, combined with operating systems that don't "block" when waiting for data, the channel controller has become somewhat redundant and are not commonly found on smaller machines.
Channel controllers can be said to be making a comeback in the form of "bus mastering" peripheral devices, such as SCSI adaptors and network cards. The rationale for these devices is the same as for the original channel controllers, namely off-loading interrupts and context switching from the main CPU.