As in NMOS logic, a collection of n-type MOSFETs is arranged in a pull-down network (PDN) between the output and the low-voltage power supply rail. However, unlike NMOS, CMOS also has a collection of p-type MOSFETs (complementary to the n-type) in a pull-up network (PUN) between the output and high-voltage rail, in place of a resistor.
As an example, here is a NOR gate in CMOS logic. Note how (in a steady state) only either the PDN or the PUN can be active at any one time. This implies there is no current flow and hence virtually no power dissipation while the circuit is at rest, a major virtue that sets CMOS circuits apart from their NMOS and TTL predecessors.
Another advantage of CMOS over NMOS is that both low-to-high and high-to-low output transitions are very fast since the transistors have low resistance when active. In addition, the output signal swings the full voltage between the low and high rails. This strong, symmetric response also makes CMOS more resistant to noise.
As switching speeds increase, though, the power dissipation of CMOS begins to be felt. This is because the currents necessary to charge and discharge the various load capacitances cause voltage drops in the transistors. Also, during transitions, for a short time both the PDN and the PUN are partially conductive, which creates direct current flow between the high- and low-voltage rails. The majority of power consumed by CMOS circuits is in fact dissipated during transitions.
CMOS circuits were invented in 1963 by Frank Wanlass at Fairchild Semiconductor. The first CMOS integrated circuits were made by RCA in 1968. Originally a low-power but slow alternative to TTL, CMOS found early adopters in the watch industry and in other fields where battery life was more important than speed.
Some twenty-five years later, CMOS has become the predominant technology in digital integrated circuits. This is essentially because area occupation, operating speed, energy efficiency and manufacturing costs have benefited and continue to benefit from the geometric downsizing that comes with every new generation of semiconductor manufacturing processes. In addition, the simplicity and comparatively low power dissipation of CMOS circuits have allowed for integration densities not possible on the basis of bipolar junction transistors.
Early CMOS circuits were very susceptible to damage from electrostatic discharge (ESD). Subsequent generations were thus equipped with sophisticated protection circuitry that helps absorb electric charges with no damage to the fragile gate oxides and pn-junctions. Still, antistatic handling precautions continue to be enforced to prevent excessive energies from building up. Please remember this when when adding a memory module to your computer, for instance.
Conversely, early generations such as the 4000 series that used aluminum as gate material were extremely tolerant to supply voltage variations and operated anywhere from 3 to 18 volts DC. Later generations use polycrystalline silicon ("polysilicon") as gate material. For many years, CMOS logic has been designed to operate from the then industry-standard of 5V imposed by TTL. Starting in the mid 1990's, it proved necessary to downscale the supply voltage along with the geometric dimensions to maintain sustainable electric fields and to improve energy efficiency. Modern CMOS circuits operate from voltages as low as 1V.
History