Instructions in a pipelined processor are performed in several stages, so that at any given time several instructions are being executed, and instructions may not be completed in desired order.
A hazard occurs when two or more of these simultaneous (possibly out of order) instructions conflict.
Table of contents |
2 Structural Hazards 3 Branch Hazards 4 Eliminating Hazards |
Data Hazards
Data hazards occur when data is modified. There are three situations it can occur in:
Structural Hazards
A structural hazard occurs when a part of the processor's hardware is needed by two or more instructions at the same time. A structural hazard might occur, for instance, if a program were to execute a branch instruction followed by a computation instruction. Because they are executed in parallel, and because branching is typically slow (requiring a comparison, program counter-related computation, and writing to registers), it is quite possible (depending on architecture) that the computation instruction and the branch instruction will both require the ALU at the same time.
This can result in the processor doing unwanted actions.
Branch Hazards
Branching hazards occur when the processor is told to branch - IE, if a certain condition is true, jump from one part of the instructions to another one - not necessarily the next one sequentially. In such a case, the processor cannot tell in advance whether or not it should process the next instruction (when it may instead have to move to a distant instruction). Eliminating Hazards
There are several established techniques for either (a) preventing hazards from occurring, or (b) working around them if they do.