Modified versions of the 1620 were used as the CPU of the IBM 1710 and IBM 1720 Industrial Process Control Systems.
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2 Development History 3 External link |
It was a variable "word" length decimal (BCD) computer with a memory that could hold anything from 20,000 to 60,000 decimal digits increasing in 20,000 decimal digit increments. While the 5-digit addresses could have addressed 100,000 decimal digits, no machine larger than 60,000 decimal digits was ever built.
Memory was accessed 2 decimal digits (Even-Odd digit pair for numeric data or 1 Alphameric character for text data) at the same time. Each decimal digit was 6-bits, composed of an odd parity Check bit, a Flag bit, and 4 BCD bits for the value of the digit in the following format:
The 1620's Architecture
C F 8 4 2 1
The Flag bit had several uses:
In addition to the valid BCD digit values there were three special digit values (these could NOT be used in calculations):
C F 8 4 2 1
1 0 1 0 - Record Mark (right most end of record)
1 1 0 0 - Numeric Blank (blank for punched card output formatting)
1 1 1 1 - Group Mark (right most end of a group of records for disk I/O)Instructions were fixed length (12 decimal digits), consisting of a 2-digit "OP Code", a 5-digit "P Address", and a 5-digit "Q Address".
Fixed point data "words" could be any size from 2 decimal digits up to all of memory not used for other purposes.
Floating point data "words" (using the hardware floating point option) could be any size from 4 decimal digits up to 102 decimal digits (2 digits for the exponent and 2 to 100 digits for the mantissa).
The machine had no programmer accessible registers: all operations were memory to memory (including the index registers of the 1620 II).
There were two models of the 1620, having totally different implementations:
Available peripherials were:
Most of the logic circuitry of the 1620 was a type of resistor-transistor logic (RTL) using "drift" transistors (a type of transistor invented by Herbert Kroemer in 1957) for their speed, that IBM referred to as SDTRL. Other IBM circuit types used were referred to as: Alloy (some logic, but mostly various non-logic functions, named for the kind of transistors used), CTRL (another type of RTL, but slower than SDTRL), CTDL (a type of diode-transistor logic (DTL)), and DL (another type of RTL, named for the kind of transistor used, "drift" transistors).
These circuits were constructed of individual discrete components mounted on single sided paper-phenolic printed circuit boards about 3 inches wide by 5 inches tall with a 16 pin edge connector, that IBM referred to as SMS cards (Standard Module System). The amount of logic on one card was similar to that in one 7400 series SSI or MSI package (e.g., 3 to 5 logic gates or a couple of flip-flops).
These boards were inserted in sockets on racks, that IBM referred to as gates. The machine had the following "gates" in its basic configuration:
In 1958 IBM assembled a team at the Poughkeepsie, New York development laboratory to study the "small scientific market". Initially the team consisted of Wayne Winger (Manager), Robert C. Jackson, and William H. Rhodes.
The competing computers in this market were the Librascope LGP-30 and the Bendix G-15, both were drum memory machines and it was concluded that IBM could offer nothing really new in that area. To compete effectively would require use of technologies that IBM had developed for larger computers, yet the machine would have to be produced at the least possible cost.
To meet this objective, the team set the following requirements:
The team expanded with the addition of Anne Deckman, Kelly B. Day, William Florac, and James Brenza. They completed the CADET prototype in the spring of 1959.
Meanwhile the San Jose, California facility was working on a proposal of its own. IBM could only build one of the two and the Poughkeepsie proposal won because "the San Jose version is top of the line and not expandable, while your proposal has all kinds of expansion capability - never offer a machine that cannot be expanded".
Management was not entirely convinced that core memory could be made to work in small machines, so Gerry Ottaway was loaned to the team to design a drum memory as a backup. During acceptance testing by the Product Test Lab repeated core memory failures were encountered and it looked likely that management's predictions would come true. However at the last minute it was found that the fan used to blow hot air through the core stack was malfunctioning, causing the core to pick up noise pulses and fail to read correctly. After the fan problem was fixed there were no further problems with the core memory and the drum memory design effort was discontinued as unnecessary.
| IBM 1620 Model I Level A (prototype), as it appeared in the IBM announcement of the machine. |
Following transfer to San Jose, someone there suggested that the code name CADET actually stood for "Can't Add, Doesn't Even Try." This stuck and became very well known among users of the 1620.
Implementation "Levels" of the IBM 1620
Patents
External link