In theory, it's possible for CMS to be modified to handle other instruction streams (i.e. to emulate other microprocessors) but this is not likely to happen anytime soon, since it's probable that the current hardware has been optimized for x86.
The addition of an abstraction layer between the x86 instruction stream and the hardware means that the hardware architecture can change without breaking x86-compatability, just by modifying CMS. For example, the second-generation Crusoe has a 256-bit wide VLIW core versus 128-bit in the first generation.
Crusoe performs in software some of the functionality traditionally implemented in hardware (e.g. instruction re-ordering), resulting in simpler hardware with fewer transistors. The relative simplicity of the hardware means that Crusoe consumes less power (and therefore generates less heat) than other x86-compatible microprocessors running at the same frequency.
There is some controversy over the performance of Crusoe relative to other x86-compatible microprocessors. The overhead associated with the software abstraction layer is supposed to be absorbed by run-time optimisations that CMS is able to make to the x86 instruction stream, but this is only true for code sequences which are repeated many times (and maybe not even then). Benchmark scores for Crusoe are generally lower than for comparable AMD or Intel processors, but it may that the subjective user experience of Crusoe performance is 'good enough', particularly in the small mobile computers aka. Subnotebooks in which Crusoe has been most widely used.