The technology behind the TM series of micro-processors is fascinating, even if the end result (from a performance perspective) was not so stunning. The actual TM processors are actually very simple VLIW cores. In order to execute x86 code, a pure software based instruction translator would, on-demand, dynamically compile or emulate executing x86 code sequences on the fly, using execution-hotspot guided heuristics. While similar technologies existed (WABI for Sun, FX!32 for Alpha) in the early 90s, the TM approach set a much higher bar for compatibility -- able to execute *all* x86 instructions from initial boot up to the latest multimedia instructions -- while retaining most of its core performance.
There are many technical benefits to Transmeta's approach: 1) As the market leaders Intel and/or AMD would extend the core x86 instruction set, Transmeta could quickly upgrade their product with a software upgrade rather than requiring a respin of their hardware. 2) If there were flaws in the hardware, the software could work around them rather than losing time in having to constantly be respinning the hardware. 3) Without all the x86 baggage built into the hardware, more time could be spent concentrating on enhancing the capabilities of the core or reducing its power consumption without worrying about backward compatibility or other instruction set constraints. 4) The processor could emulate multiple other architectures, possibly even at the same time (at its initial Crusoe launch, Transmeta demonstrated pico-Java and x86 running intermixed on the native hardware.)
These capabilities seem to confirm the possibilities indicated by some of the rumors flying around prior to the release of Crusoe (that they were building a hybrid PowerPC and x86 processor -- something they certainly could have done, and which they may have intially been planning, for example.) However, Transmeta has decided to concentrate solely on the extreme low power x86 market.
During August, 2003, Transmeta's debuted its latest chip, the Efficeon.